1. Technical Field
The present invention relates generally to an improved data processing system and, in particular, to a method and apparatus for instruction processing architecture and instruction processing control within a processor in a data processing system, and more particularly, processing control with specialized instruction processing in support of testing and debugging.
2. Description of Related Art
Modern processors commonly use a technique known as pipelining to improve performance. Pipelining is an instruction execution technique that is analogous to an assembly line. Instruction execution often involves the sequential steps of fetching the instruction from memory, decoding the instruction into its respective operation and operand(s), fetching the operands of the instruction, applying the decoded operation on the operands (herein simply referred to as xe2x80x9cexecutingxe2x80x9d the instruction), and storing the result back in memory or in a register. Pipelining is a technique wherein the sequential steps of the execution process are overlapped for a subsequence of the instructions. For example, while the CPU is storing the results of a first instruction of an instruction sequence, the CPU simultaneously executes the second instruction of the sequence, fetches the operands of the third instruction of the sequence, decodes the fourth instruction of the sequence, and fetches the fifth instruction of the sequence. Pipelining can thus decrease the execution time for a sequence of instructions.
Another technique for improving performance involves executing two or more instructions in parallel, i.e., simultaneously. Processors that utilize this technique are generally referred to as superscalar processors. Such processors may incorporate an additional technique in which a sequence of instructions may be executed out of order. Results for such instructions must be reassembled upon instruction completion such that the sequential program order or results are maintained. This system is referred to as out-of-order issue with in-order completion.
The ability of a superscalar processor to execute two or more instructions simultaneously depends upon the particular instructions being executed. Likewise, the flexibility in issuing or completing instructions out-of-order can depend on the particular instructions to be issued or completed. There are three types of such instruction dependencies, which are referred to as: resource conflicts, procedural dependencies, and data dependencies. Resource conflicts occur when two instructions executing in parallel tend to access the same resource, e.g., the system bus. Data dependencies occur when the completion of a first instruction changes the value stored in a register or memory, which is later accessed by a later completed second instruction.
During execution of instructions, an instruction sequence may fail to execute properly or to yield the correct results for a number of different reasons. For example, a failure may occur when a certain event or sequence of events occurs in a manner not expected by the designer. Further, an error also may be caused by a misdesigned circuit or logic equation. Due to the complexity of designing an out-of-order processor, the processor design may logically mis-process one instruction in combination with another instruction, causing an error. In some cases, a selected frequency, voltage, or type of noise may cause an error in execution because of a circuit not behaving as designed. Errors such as these often cause the scheduler in the microprocessor to xe2x80x9changxe2x80x9d, resulting in execution of instructions coming to a halt. Even worse, these errors can cause the processor to obtain an incorrect answer or to corrupt the data being processed.
Once an error is diagnosed, it may be difficult to introduce a repair or patch that allows the processor, which has already been manufactured, to continue operating such that it does not repeatedly encounter the diagnosed error.
Therefore, it would be advantageous to have a method and apparatus for preventing processing errors in an operational microprocessor in spite of errors or flaws in a hardware design.
A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instruction. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. A matched instruction may be marked using a match bit that accompanies the instruction through the instruction pipeline. The matched instruction is then replaced with an internal opcode or internal instruction that causes the instruction scheduling unit to take a special software interrupt. The problematic instruction is then patched through the execution of a set of instructions that cause the desired logical operation of the problematic instruction.